1. Field of the Invention
This invention relates to processes for fabricating integrated circuits, and to processes for fabricating both bipolar and complementary field effect transistors in the same substrate. In particular, the invention relates to a BiCMOS process in which selective formation of an epitaxial layer is employed to isolate individual bipolar and CMOS transistors, as well as other components.
2. Description of the Prior Art
Bipolar and CMOS technologies have each been independently understood for many years. Recently, however, the ability to combine CMOS with bipolar on the same integrated circuit has raised new possibilities for very large scale integration. For example, bipolar output drivers may be employed with CMOS memories to provide more drive current. Because normally MOS circuits operate slower with increasing temperature, while bipolar operates faster, a CMOS bipolar combination may be employed to make devices less speed sensitive to temperature. In addition, combining high performance bipolar devices with MOS transistors on the same integrated circuit allows a combination of the high-packing density of MOS devices and permits the ability to integrate complex functions with high yields. The CMOS circuits have inherently low power requirements, while the bipolar devices have an advantage in switching speed and current drive per unit area.
Accordingly, much effort has been devoted by process scientists and engineers toward methods of integrating bipolar and CMOS processes on a single wafer. Unfortunately, such processes are generally not optimized for either the CMOS aspect or the bipolar aspect, consisting instead of a brute force combination of the steps required to fabricate each type device with all of its associated process steps. The result is a lengthy and complicated process using a large number of masking operations, which is vulnerable to lower yields as a result of the complexity of the process.
Most such prior art processes are basically either a CMOS or a bipolar process, that is, the CMOS process provides little for the ad hoc bipolar devices as they end up being built from CMOS spare parts and display lackluster performance. As a result, the compromised technology cannot compete on its own against processes optimized for either of the constituent bipolar or CMOS devices. Typical prior art bipolar-CMOS processes may be found in U.S. Pat. No. 4,484,388 to Iwasaki; U.S. Pat. No. 4,507,847 to Sullivan; and U.S. Pat. No. 4,536,945 to Gray et al.; and U.S. Pat. No. 3,955,269 to Magdo et al.